1. Field of the Invention
The present invention relates to semiconductor test structures, and more specifically to a semiconductor test structures that is formed in a cutting path of a semiconductor wafer.
2. Description of Related Art
Conventionally, a plurality of integrated circuits are formed in predetermined zones of a circular semiconductor wafer. The zones of the wafer are delimited by cutting paths along which the wafer is subsequently sliced to separate the individual integrated circuits. Before cutting the wafer and simultaneous with the formation of the integrated circuits, test structures are also formed in the silicon, typically in the vicinity of the cutting paths. Such test structures generally include chains of inverters having transistors of different widths and lengths associated with capacitive loads made from gate oxides, and each inverter cell is repeated so as to form an oscillating ring. The output frequency of the oscillating ring is divided to allow measurement at low frequency (e.g., 1 MHz). The frequency measurement allows monitoring of the characteristics of the transistors of the test structure, and thus allows indirect monitoring of the characteristics of the transistors of the integrated circuits adjacent to the test structure. Additionally, the test structures can be used to validate electrical simulation models. However, conventional test structures do not allow measurement of the influence of the interconnection resistances and capacitances that exist in the integrated circuits.